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Design of all-optical half-adder based on nonlinear effect and linear interference effect

YANG Jian-ye WU Rong ZHANG Hao-chen

杨建业, 吴蓉, 张皓辰. 结合非线性效应和线性干涉效应设计的全光半加器[J]. , 2023, 16(5): 1186-1194. doi: 10.37188/CO.EN.2022-0029
引用本文: 杨建业, 吴蓉, 张皓辰. 结合非线性效应和线性干涉效应设计的全光半加器[J]. , 2023, 16(5): 1186-1194. doi: 10.37188/CO.EN.2022-0029
YANG Jian-ye, WU Rong, ZHANG Hao-chen. Design of all-optical half-adder based on nonlinear effect and linear interference effect[J]. Chinese Optics, 2023, 16(5): 1186-1194. doi: 10.37188/CO.EN.2022-0029
Citation: YANG Jian-ye, WU Rong, ZHANG Hao-chen. Design of all-optical half-adder based on nonlinear effect and linear interference effect[J]. Chinese Optics, 2023, 16(5): 1186-1194. doi: 10.37188/CO.EN.2022-0029

结合非线性效应和线性干涉效应设计的全光半加器

详细信息
  • 中图分类号: TN256

Design of all-optical half-adder based on nonlinear effect and linear interference effect

doi: 10.37188/CO.EN.2022-0029
Funds: Supported by Natural Science Foundation of Gansu Province (No. 21JR7RA289)
More Information
    Author Bio:

    Yang Jian-ye (1999—), male, born in Zhouqu County, Gansu Province, postgraduate. Received a Bachelor of Engineering degree from Lanzhou Jiaotong University in June 2021. Mainly engaged in research on mode division multiplexing integrated devices and all optical logic devices. E-mail: 1114332211@qq.com

    Corresponding author: 1114332211@qq.com
  • 摘要:

    结合光子晶体非线性效应和线性干涉效应设计了一种全光半加器。将光源平均分成两部分,对半加器的与门和异或门分开设计。利用非线性效应实现高对比度的与门;利用线性干涉效应实现异或逻辑,从而使器件整体响应速度更快。在这种设计结构下,器件对信号光源功率只有阈值要求,当信号功率大于51.4 mW/μm2时输出稳定,抗干扰能力强。所设计的半加器进位输出端口对比度为20.69 dB,输出端口对比度为20.13 dB。数据传输速率为0.75 Tbits/s,占用面积623 μm2

     

  • Figure 1.  Characteristics of nonlinear annular cavity. (a) Structure of nonlinear annular cavity. (b) Normalized power of output port in the band of 1.52−1.58 μm

    Figure 2.  Normalized output port powers at (a) low power incidence and (b) high power incidence

    Figure 3.  (a) XOR gate structure. (b) Steady state electric field diagram when input is logic '11'

    Figure 4.  Half-adder structure

    Figure 5.  Half-adder normalized power output curve. (a) Input is logical '01'. (b) Input is logical '10'. (c) Input is logical '11'

    Figure 6.  Optimized half-adder structure

    Figure 7.  Steady state diagram of half-adder electric field. (a) Input is logical '01'. (b) Input is logical '10'. (c) Input is logical '11'

    Figure 8.  Normalized power output curve. (a) Input is logical '01'. (b) Input is logical '10'. (c) Input is logical '11'

    Figure 9.  Influence of light source power on output. (a) Impact on CARRY output. (b) Impact on SUM output

    Table  1.   The output parameters of the latter half-adder

    Input (Normalized power) Output (Normalized power)
    A B CARRY SUM
    0 1 7.9×10−3 0.512
    1 0 7.8×10−3 0.505
    1 1 0.926 4.9×10−4
    下载: 导出CSV

    Table  2.   Summarized features of proposed structure and previous works

    Works SUM
    contrast (dB)
    CARRY
    contrast (dB)
    Bit rate
    (Tbps)
    Footprint
    (μm2)
    Ref[18] 9.30 8.22 4.55 138
    Ref[19] 8.40 9.29 6.67 192
    Ref[20] 5.64 5.29 1.25 130
    This work 20.13 20.69 0.75 623
    下载: 导出CSV
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出版历程
  • 收稿日期:  2023-01-04
  • 修回日期:  2023-02-22
  • 网络出版日期:  2023-03-17

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