利用DSP底层结构提高MPEG-4编码的实时性 -

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利用DSP底层结构提高MPEG-4编码的实时性

李桂菊

中国科学院长春光学精密机械与物理研究所,吉林长春 130033

基金项目:

国家自然科学基金资助项目(No.60805045)

详细信息

作者简介:
李桂菊(1964-),女,吉林市人,研究员,主要从事DSP开发与应用等方面的研究。 E-mail:lgjciom666@yahoo.com.cn

中图分类号:TN919.81
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出版历程
- 收稿日期:2011-07-13
- 修回日期:2011-08-23
- 刊出日期:2011-10-25

Improvement of real-time properties of MPEG-4 encoder by DSP underlying structure

LI Gui-ju

Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences, Changchun 130033, China

摘要

摘要:由于利用TMS320C6000系列的DSP底层结构可以提高图像压缩的实时性,本文在TMS320C6416平台上针对DSP底层结构对MPEG-4视频编码进行了优化,包括对8个运算单元能并行执行的特性进行汇编。针对DSP芯片两级高速缓存的工作特点,对编码器中代码和数据所占用的内存空间进行优化。利用EDMA级联特性在内存开辟双缓冲区,同时完成视频数据编码和传输的工作,从而有效地改善编码效率。实验结果表明:该编码器可以对512 pixel512 pixel大小的灰度图像,以30 frame/s帧频进行压缩,实现了对视频图像的实时编码。
- 视频压缩/
- 数字信号处理器/
- 软件优化
Abstract:As the real time properties of image compression can be improved by utilizing a DSP underlying structure, this paper optimizes the Mpeg-4 video encoder on a TMS320C6416 platform by the structure mentioned above. Optimizing methods include complying the assembly functions according to the characteristics of eight parallel execution functional units, optimizing the code and data memory space occupied by the encoder according to the features of DSP two-level cache, and adapting two buffers in memory by using the EDMA cascade characteristics to realize video data coding and transmission at the same time, which improves coding efficiency effectively. The experimental results show that the new encoder can realize encoding of gray scale video of 512 pixel512 pixel at 30 frame/s in real time.
- video compression/
- digital signal processor/
- software optimization

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参考文献 (1)

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