Integrated silicon waveguide electro-optic half-adder based on Epsilon-Near-Zero and ITO
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摘要:为了解决传统电光混合运算逻辑单元速率低、功耗高、尺寸大等问题，以实现电光混合高速运算，本文设计了一种基于介电常数近零态（Epsilon-Near-Zero）和铟锡氧化物（ITO）薄膜电调控的集成硅基波导电光混合半加器。利用ITO激活材料薄膜的电调控特性实现了光路通断和交叉，从而实现了两位二进制数的半加法功能，通过3D-FDTD模拟仿真对器件模型结构参数进行了优化设计。仿真实验结果表明，当施加电压为0 V和2.35 V时，器件能够完成光信号逻辑控制。电光混合半加器工作在1550 nm波长时，其插入损耗为0.63 dB，消光比为31.73 dB，数据传输速率为61.62 GHz，每字节消耗能量为13.44 fJ，整个半加器尺寸小于21.3 μm×1.5 μm×1.2 μm。该器件具有结构紧凑、插入损耗低等特点，为高速电光混合光学逻辑器件及半加器设计提供了理论依据。Abstract:In order to achieve high-speed electro-optic hybrid operation of half-adders and solve their disadvantages in speed, energy consumption and size, a silicon waveguide integrated electro-optic half-adder is designed based on an Epsilon-Near-Zero and ITO electrical-tunable film. The ITO electrical-tunable film is used as the switch for the optical path, and thus achieve the half-add function of two binary numbers. Simulation results show that the device unit can complete the optical signal logic control when the applied voltage is 0 V and 2.35 V. When the hybrid electro-optic half-adder works at a wavelength of 1550 nm, the insertion loss is 0.63 dB, the extinction ratio is 31.73 dB, the data transmission rate is 61.62 GHz, the energy consumption per bit is 13.44 fJ, and the size of the whole half-adder is less than 21.3 μm×1.5 μm×1.2 μm. The device is compact and has a low insertion loss. This provides a theoretical foundation for the design of high-speed hybrid electro-optic logic devices and half-adders.
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图 1半加器模型及其电极示意图。（a）半加器平面俯视图（b）半加器3D模型（c）半加器器件加电极方案平面俯视图（d）半加器器件加电极方案3D模型
Figure 1.Schematic diagram of the proposed electro-optic half-adder model and its electrode. (a) Top view of the half-adder; (b) 3D model of the half-adder; (c) top view of the half-adder with electrode; (d) 3D model of the half-adder with electrode
图 2ITO薄膜施加电压模型简图及其特性。（a）施加电压模型；（b）模型等效电路；（c）模型等效电路简化图；（d）施加0~4 V电压时，载流子浓度的变化情况；（e）ITO的复合介电常数随电压的变化情况
Figure 2.Schematic diagram of ITO film's applied voltage and its charateristics. (a) The model of applied voltage; (b) equivalent circuit; (c) simplification of the equivalent circuit; (d) variation of carrier concentration when applied voltage is 0~4 V; (e) relationship between the real (green line) and imaginary (red line) components of the complex permittivity ITO as a function of the gating voltage.
图 3（a）光信号直通逻辑控制单元；（b）施加电压情况下，光信号直通逻辑控制单元ON状态下的电磁场分布情况；（c）未施加电压情况下，光信号直通逻辑控制单元OFF状态下的电磁场分布情况；（d）光信号交叉逻辑控制单元；（e）施加电压情况下，光信号交叉、直通逻辑控制单元为交叉状态；（f）未施加电压情况下，光信号交叉、直通逻辑控制单元为直通状态
Figure 3.(a) Straight logic control unit for the optical signal; electromagnetic field distribution of straight logic control unit under ON state (b) and (c) OFF state; (d) BAR and CROSS logic control unit; (e) CROSS state of BAR and CROSS logic control unit with a voltage applied; (f) BAR state of BAR and CROSS logic control unit without a voltage applied
图 4ON和OFF状态下的透射率和ER随ITO的变化情况
Figure 4.Transmission andERvary with different ITO thickness in ON and OFF states
图 5ON和OFF状态下的透射率和ER随SiO2厚度的变化情况
Figure 5.Transmission andERvary with thickness of SiO2in ON and OFF states
图 6ON和OFF状态下的透射率和ER随Lc1的变化情况
Figure 6.Transmission andERvary withLc1in ON and OFF states
图 7ON和OFF状态下透射率和ER随Lc2的变化情况
Figure 7.Transmission andERvary withLc2in ON and OFF states
图 9ON和OFF状态下透射率和ER随gap的变化情况
Figure 9.Transmission andERvary with gap in ON and OFF states
图 10逻辑控制区域施加不同逻辑控制时半加器器件的仿真电磁场分布图。
Figure 10.The electric field distribution of the half-adder under different biasing conditions
图 12100 Gbit/s数据传输速率下的动态响应图
Figure 12.Dynamic response waveform when the data transmission rate is 100 Gbit/s
表 1器件模型最优化参数
Table 1.Optimized parameters of the device model
Parameters Values/nm ITO 15 SiO2 14 gap 140 Lc1 1350 Lc2 8700 
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表 2两位二进制加法功能真值表
Table 2.Truth table of the half-adder
input sum carry x y 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 1 下载:
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表 3电光半加器性能参数
Table 3.The performance parameters of the electro-optical half-adder
iput sum carry ER/（dB） IL/（dB） x/V y/V 0 0 0.00035 0.00026 \ \ 2.35 0 0.54762 0.00021 34.7387 0.57609 0 2.35 0.54081 0.00019 35.1733 0.63044 2.35 2.35 0.00038 0.56622 31.7320 0.43103 下载:
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