双抽头CCD图像整合优化设计 -

姓名
邮箱
手机号码
标题
留言内容
验证码

双抽头CCD图像整合优化设计

doi:10.3788/CO.20120501.0042

1.
中国科学院长春光学精密机械与物理研究所,吉林长春 130033;
2.
中国科学院研究生院,北京 100039

基金项目:

国家自然科学基金资助项目(No.61036015)

详细信息

作者简介:
李洪法(1979-),男,山东莱州人,硕士,助理研究员,主要从事CCD成像技术方面的研究。 E-mail:lihongfa99058@163.com

中图分类号:TP391; TN386.5
计量
- 文章访问数:3066
- HTML全文浏览量:457
- PDF下载量:963
- 被引次数:0
出版历程
- 收稿日期:2011-10-15
- 修回日期:2011-11-13
- 刊出日期:2012-02-10

Optimization design of image conformity for double-tap CCD

1.
Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences, Changchun 130033, China;
2.
Graduate University of Chinese Academy of Sciences, Beijing 100039, China

摘要

摘要:为了解决双抽头CCD输出图像顺序不一致的问题,提出了一种改进的RAM软件设计方法,并对其数据进行重新整合。首先,利用XILINX VIRTEX系列现场可编程门阵列(FPGA)的内部Block RAM构造形成双端口RAM。其次,利用双抽头CCD的第一个抽头数据在整合前后没有变化的特点,改进了传统的乒乓操作方法,实现了对整片CCD输出的整合。与传统的图像整合方法相比,该方法对硬件的资源占用率节省了25%。利用ModelSim软件对该方法进行仿真实验,验证了其正确性和有效性。该方法节约了硬件资源,降低了硬件成本,并已成功应用在实际工程项目中。
- 双抽头CCD/
- 图像整合/
- 现场可编程门阵列/
- ModelSim软件
Abstract:In order to modify the disaccord of output sequency of a double-tap Charge Coupled Device(CCD), an improved design method for software RAM is proposed, and the output of CCD is conformed by this method. Firstly, a dual-port RAM is constructed by using Block RAM of Xilinx Virtex series Field Programmable Gate Array(FPGA). Since the sequence of data from tap1 is the same as that to be conformed before, this paper comes up with an improved method based on the traditional Ping-Pang operation to conform the output data from the CCD. Comparing to the traditional Ping-Pang method, the resource consumption of designed software is greatly reduced by 25%. It is proved to be valid and accurate by the simulation result of ModelSim. The new method which has been applied in the project successfully can save hardware resources and reduce the hardware cost greatly.
- double-tap CCD/
- image conformity/
- Field Programmable Gate Array(FPGA)/
- ModelSim software

HTML全文

参考文献 (1)

[1] 胡琳. CCD图像传感器的现状及未来发展[J]. 电子科技,2010,23(6):82-85. HU L. Current situations and future developments of CCD image sensors[J].Electronic Sci.&Technology,2010,23(6):82-85.(in Chinese) [2] HIDESHI A. Device technologies for high quality and smaller pixel in CCD and CMOS image sensors //Proceeding of the Technical Digest International Electron Devices Meeting,2004:989-912. [3] THEUWISSEN A J P. The hole role in solid-state imagers[J].IEEE T. Electron Devices,2006,53(12):2972-2980. [4] 王明富,杨世洪,吴钦章. 大面阵CCD图像实时显示系统的设计[J]. 光学精密工程,2010,18(9):2053-2059. WANG M F,YANG SH H,WU Q ZH. Design of large-array CCD real-time display system[J].Opt. Precision Eng.,2009,17(8):2053-2059.(in Chinese) [5] 徐欣,于红旗,易凡,等.基于FPGA的嵌入式系统设计[M]. 北京:机械工业出版社,2004. XU X,YU H Q,YI F,et al. Embedded System Design Based on FPGA[M]. Beijing:China Machine Press,2004.(in Chinese) [6] 周贤波,冯龙龄. 基于DSP和FPGA 图像采集技术的研究[J]. 光学技术,2006,32(增):141-143. ZHOU X B,FENG L L. A study on image acquisition technology based on DSP and FPGA[J].Opt. Technique,2006,32(S):141-143.(in Chinese) [7] 梁冰,易茂祥,颜天信. 高性能线性CCD开发平台的研制[J]. 合肥工业大学学报 (自然科学版),2010,33(10):1579-1581. LIANG B,YI M X,YAN T X. Design of high-performance linear CCD development platform[J].J. Hefei University Technol.,2010,33(10):1579-1581.(in Chinese) [8] DUAN J H,DENG Y L,LANG K. Development of image processing system based on DSP and FPGA,ICEMI'07. 8th Int Conf on Electronic Measurement and Instruments,Aug 16-18 2007,Xi'an,China,2007:2791-2794. [9] ZHANG F. A high-speed method of CCD image data storage system[J].IEEE Advanced Computer Control,2010,2(6):45-48. [10] ZHAO Y F,WANG Q Y. Digital image storage system based on 1M60 digital CCD[J].Electronics&Control,2007,14(5):179-183. [11] 王文华,何斌,任建岳. 线阵CCD成像系统自校图形设计[J]. 光学精密工程,2009,17(8):2011-2016. WANG W H,HE B,REN J Y. Design of self-check figures in linear CCD imaging system[J].Opt. Precision Eng.,2009,17(8):2011-2016.(in Chinese)

施引文献

附加信息 (0)

访问统计