Mar. 2014

Article Contents

Chinese Optics> 2014> 7(2): 225-233.

CHEN Ying, ZHU Ming. Multiple sub-histogram equalization low light level image enhancement and realization on FPGA[J]. Chinese Optics, 2014, 7(2): 225-233. doi: 10.3788/CO.20140702.0225

Citation:

CHEN Ying, ZHU Ming. Multiple sub-histogram equalization low light level image enhancement and realization on FPGA[J].Chinese Optics, 2014, 7(2): 225-233.doi:10.3788/CO.20140702.0225

CHEN Ying, ZHU Ming. Multiple sub-histogram equalization low light level image enhancement and realization on FPGA[J]. Chinese Optics, 2014, 7(2): 225-233. doi: 10.3788/CO.20140702.0225

Citation:

CHEN Ying, ZHU Ming. Multiple sub-histogram equalization low light level image enhancement and realization on FPGA[J].Chinese Optics, 2014, 7(2): 225-233.doi:10.3788/CO.20140702.0225

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Multiple sub-histogram equalization low light level image enhancement and realization on FPGA

doi:10.3788/CO.20140702.0225

CHEN Ying^1,2,
ZHU Ming^1,,

1.
Key Laboratory of Airborne Optical Imaging and Measurement, Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences, Changchun 130033, China;
2.
University of Chinese Academy of Sciences, Beijing 100049, China

Received Date:10 Nov 2013
Rev Recd Date:08 Feb 2014
Publish Date:25 Mar 2014

Abstract

Abstract

In order to solve the problems that low light level image has low contrast and it is difficult to distinguish objective, it is necessary to research on low light level image enhancement algorithm. A multiple sub-histogram equalization enhancement algorithm is proposed. Initially, in the proposed algorithm, the histogram are separated into four parts according to the area equally. Then, the resultant sub-histograms are clipped according to the average number of pixels of input image to reduce the enhancement phenomenon. In addition, the scale factor is adopted to adjust dynamic range. Finally, each sub-histogram is equalized. The algorithm is implemented on FPGA with verilog language, and is given subjective and objective evaluation. With this algorithm good results can be achieved in real-time on the hardware platform, and the delay of an image processing is about 0.45 ms. Experimental results show that with this proposed algorithm no saturation and noise amplification phenomenon appear, and image details of the processed image are well preserved and highlighted. The algorithm meets the real-time requirement and the enhanced images of better visual effect can be achieved.
- image enhancement,
- histogram equalization,
- low light level image,
- FPGA,
- real time

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References (1)

References

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